1. Field of the Invention
The invention relates to a stable memory circuit and to a computer incorporating such a circuit.
The term "stable memory" is intended to cover memory, the contents of which is not corrupted under fault conditions such as power failure or faulty processor operation and with which atomic stable memory operations may be performed.
2. Prior Art
Heretofore, stable storage has often been achieved by use of duplicated peripheral storage devices such as disks to which data is regularly copied. Verification operations are carried out to ensure that the copy operations have been correctly carried out to each of the peripheral storage devices in turn. The copy and verification sequence is called an atomic transaction since it is designed only to succeed or fail- no other result is allowed, and failure does not result in corruption of data. The major problem with this arrangement is that operation of a processor is significantly slowed down because transmission of data and instructions to the peripheral storage devices takes a significant amount of time.
In another approach such as that described in U.S. Pat. No. 4,799,186 (PLOYETTE) stable memory is provided by duplicated on-board memory circuits. This results in less time being required by the processor to perform the atomic transactions, both because memory circuits are generally much faster than peripheral storage circuits and because the sequence of operations may be carried out by a controller within the stable memory circuit itself. However, there is still a significant use of processor time because the stable memory circuit acts as a peripheral storage device that must have data copied to it from conventional memory, and it cannot act as conventional memory at any time, even when stable memory operation is not required.